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| NJW1110 9-IN 3-OUT STEREO AUDIO SELECTOR ! GENERAL DESCRIPTION NJW1110 is a 9-input 3-output stereo audio selector. It includes three independent 9input-1output stereo audio selectors and adjustable gain buffers. NJW1110 performs superior audio characteristics such as low distortion, low output noise and low crosstalk. All of internal status and variables are 2 controlled by I C BUS interface. And the slave address selector is available for using two chips on same serial Bus line. It is suitable for latest TV system and others. ! APPLICATIONS *FPD TV *Car Audio System *Monitor ! FEATURES * Operating Voltage 7.5 to 15V * Operating Current 8mA typ. * 9-Input, 3-Output Stereo Audio Selector * Low Distortion 0.0007% typ. * Low Output Noise 116dB typ. * Low Crosstalk 110dB typ. * Channel Separation 100dB typ. * Variable Gain Buffer 0, 3 to 8dB/0.5dB step 2 * I C Bus Interface (Comply with fast mode and 3V I/F) * Selectable 2-Slave Address * Bi-CMOS Technology * Package Outline SSOP32 ! BLOCK DIAGRAM InB1 InB2 InB3 InB4 InB5 InB6 InB7 InB8 InB9 OutB1 OutB2 OutB3 V+ ADR ! PACKAGE OUTLINE NJW1110V 10F + 10F + 10F + 10F + 10F + 10F + 10F + 10F + 10F + 10F + 10F + 10F + 10F + + 100F 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GND 18 17 MUTE Gain 50KX18 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Vref Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep MUTE I2C Control Logic GND GND 1 10F + 2 10F + 3 10F + 4 10F + 5 10F + 6 10F + 7 10F + 8 10F + 9 10F + 10 10F 11 + 12 10F + 13 10F + 14 15 16 InA1 InA2 InA3 InA4 InA5 InA6 InA7 InA8 InA9 OutA1 OutA2 OutA3 SDA SCL -1- NJW1110 ! ABSOLUTE MAXIMUM RATING (Ta=25C) PARAMETER SYMBOL Power Supply Voltage V + RATING 16 0 to V+ 800 () UNIT V V mW C C Maximum input voltage Power Dissipation Operating Temperature Range Storage Temperature Range () VIM PD Topr Tstg NOTE: EIA/JEDEC STANDARD Test board (76.2x114.3x1.6mm, 2layer, FR-4) mounting -40 to +85 -40 to +125 For the maximum input voltage less than V+. ! RECOMMENDED OPERATING CONDITIONS (Ta=25C) PARAMETER Operating Voltage SYMBOL V + TEST CONDITION - MIN. 7.5 TYP. 9.0 MAX. 15.0 UNIT V ! ELECTRICAL CHARACTERISTICS + Power Supply (Ta=25C, V =9V) PARAMETER Supply Current Reference Voltage SYMBOL ICC VREF + TEST CONDITION No Signal No Signal MIN. 4.0 4.0 TYP. 8.0 4.5 MAX. 12.0 5.0 UNIT MA V AC CHARACTERISTICS (Ta=25C, V =9V, VIN=0dBV (0dBV=1Vrms), f=1kHz, RL=47k) PARAMETER Maximum Output Voltage Voltage Gain 1 Voltage Gain 2 Total Harmonic Distortion 1 Total Harmonic Distortion 2 Total Harmonic Distortion 3 Output Noise Cross Talk 1 Cross Talk 2 Channel Separation 1 Channel Separation 2 SYMBOL VOM GV1 GV2 THD1 THD2 THD3 VNO CT1 CT2 CS1 CS2 TEST CONDITION THD=1% VIN=200mVrms, Gain=6dB BW=400Hz-30kHz f=10kHz, BW=400Hz-30kHz V =12V, BW=400Hz-30kHz Rg=0, A-Weighted Rg=0, A-Weighted Rg=0, f=20kHz Rg=0, A-Weighted Rg=0, f=20kHz + + MIN. 6.0 (2.0) TYP. 8.0 (2.5) MAX. 1.0 UNIT dBV (Vrms) -1.0 5.0 - 0 6.0 0.001 0.003 0.0007 -116 (1.6) dB 7.0 0.02 -106 (5.0) % dBV (Vrms) -110 -90 -110 -90 dB dB BW: Band Width Logic Control Characteristics (Ta=25C, V =9V) PARAMETER High Level Input Voltage Low Level Input Voltage SYMBOL VADRH VADRL TEST CONDITION ADR Terminal ADR Terminal MIN. 2.5 0 TYP. MAX. V + UNIT V 1.5 -2- NJW1110 ! I C BUS BLOCK CHARACTERISTICS (SDA,SCL) Standard mode : I2C BUS Load Conditions: Pull up resistance 4k (Connected to +5V), Load capacitance 200pF (Connected to GND) Fast mode : I2C BUS Load Conditions: Pull up resistance 4k (Connected to +5V), Load capacitance 50pF (Connected to GND) 2 PARAMETER Low Level Input Voltage High Level Input Voltage Hysteresis of Schmitt trigger inputs Low level output voltage (3mA at SDA pin) Output fall time from VIHmin to VILmax with a bus capacitance from 10pF to 400pF Pulse width of spikes which must be suppressed by the input filter Input current each I/O pin with an input voltage between 0.1VDD and 0.9VDDmax Capacitance for each I/O pin SCL clock frequency Hold time (repeated) START condition. Low period of the SCL clock High period of the SCL clock Set-up time for a repeated START condition Data hold time Data set-up time Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition Capacitive load for each bus line Noise margin at the Low level Noise margin at the High level SYMBOL VIL VIH Vhys VOL tof tSP Ii Ci fSCL tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tr tf tSU:STO tBUF Cb VnL Standard mode MIN. 0.0 2.7 0 -10 4.0 4.7 4.0 4.7 0 250 4.0 4.7 0.5 1 TYP. MAX. 1.5 5.0 0.4 250 10 10 100 1000 300 400 MIN. 0.0 2.7 0.25 0 Fast mode TYP. MAX. 1.5 5.0 0.4 250 50 10 10 400 300 300 400 - UNIT V V V V ns ns A pF kHz s s s s s ns ns ns s s pF V 20 +0.1Cb 0 -10 0.6 1.3 0.6 0.6 0 100 0.6 1.3 0.5 1 VnH V Cb; total capacitance of one bus line in pF. NOTE). Please hold the Data Hold Time (tHD:DAT) to 300ns or more to avoid status of unstable at SCL falling edge. SDA tBUF tR tF tHD:STA SCL tHD:STA tLOW P S tHD:DAT tHIGH tSU:DAT Sr tSU:STA tSU:STO P -3- NJW1110 ! PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 InA1 InA2 InA3 InA4 InA5 InA6 InA7 InA8 InA9 GND OutA1 OutA2 OutA3 GND SDA SCL InB1 32 InB2 31 InB3 30 InB4 29 InB5 28 InB6 27 InB7 26 InB8 25 InB9 24 Vref OutB1 OutB2 OutB3 23 22 21 20 GND 19 ADR V+ 18 16 17 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol InA1 InA2 InA3 InA4 InA5 InA6 InA7 InA8 InA9 GND OutA1 OutA2 OutA3 GND SDA SCL Function Ach Input 1 Ach Input 2 Ach Input 3 Ach Input 4 Ach Input 5 Ach Input 6 Ach Input 7 Ach Input 8 Ach Input 9 GND Terminal Ach Output 1 Ach Output 2 Ach Output 3 GND Terminal SDA Data Input (I2C BUS) SCL Clock Input (I C BUS) 2 No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol V+ ADR GND OutB3 OutB2 OutB1 Vref InB9 InB8 InB7 InB6 InB5 InB4 InB3 InB2 InB1 Function Power Supply Terminal Slave address setting terminal GND Terminal Bch Output 3 Bch Output 2 Bch Output 1 Reference Voltage Bch Input 9 Bch Input 8 Bch Input 7 Bch Input 6 Bch Input 5 Bch Input 4 Bch Input 3 Bch Input 2 Bch Input 1 -4- NJW1110 ! DEFINITION OF I C REGISTER 2 I C BUS FORMAT MSB LSB MSB LSB MSB LSB 2 S 1bit Slave Address 8bit A 1bit Select Address 8bit A 1bit Data 8bit A 1bit P 1bit S: Starting Term A: Acknowledge Bit P: Ending Term SLAVE ADDRESS MSB LSB 1 1 0 0 0 0 1 1 0 0 1 1 0 1 R/W R/W 94H(ADR=Low) 96H(ADR=High) R/W=0: Receive Only R/W=0: Write mode for register setting R/W=1: Not available CONTROL REGISTER TABLE The select address and sets each function. The auto increment function cycles the select address as follows. 00H01H02H00H BIT Select Address D7 D6 D5 D4 D3 00H 01H 02H Variable Gain Buffer for OUT1 Variable Gain Buffer for OUT2 Variable Gain Buffer for OUT3 D2 D1 D0 Input selector for OUT1 Input selector for OUT2 Input selector for OUT3 CONTROL REGISTER DEFAULT VALUE Control register default value is all "0". Select Address 00H 01H 02H BIT D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 0 D0 0 0 0 -5- NJW1110 ! INPUT SELECTOR " INPUT SELECTOR SETTING (OUT1:00H, OUT2:01H, OUT3:02H) Signal Select Mute InA1/InB1 InA2/InB2 InA3/InB3 InA4/InB4 InA5/InB5 InA6/InB6 InA7/InB7 InA8/InB8 InA9/InB9 D3 0 0 0 0 0 0 0 0 1 1 D2 0 0 0 0 1 1 1 1 0 0 D1 0 0 1 1 0 0 1 1 0 0 D0 0 1 0 1 0 1 0 1 0 1 ! VARIABLE GAIN BUFFER " VARIABLE GAIN BUFFER SETTING (OUT1:00H, OUT2:01H, OUT3:02H) Gain (dB) 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 D7 0 0 0 0 0 0 0 0 1 1 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 D5 0 0 1 1 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 0 1 0 1 -6- NJW1110 ! APPLICATION CIRCUIT InB1 InB2 InB3 InB4 InB5 InB6 InB7 InB8 InB9 OutB1 OutB2 OutB3 V+ ADR 10F + 10 F + 10F + 10F + 10F + 10F + 10 F + 10F + 10F + 10F + 10 F + 10 F + 10F + + 100 F 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GND 18 17 MUTE Gain 50KX18 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Vref Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep Gain 8dB to 3dB / 0.5dBstep MUTE I2C Control Logic GND GND 1 10F + 2 10 F + 3 10F + 4 10F + 5 10F + 6 10F + 7 10 F + 8 10F + 9 10F + 10 10 F 11 + 12 10 F + 13 10F + 14 15 16 InA1 InA2 InA3 InA4 InA5 InA6 InA7 InA8 InA9 OutA1 OutA2 OutA3 SDA SCL [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. -7- |
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